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altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示
altera_sdram
- SDRAM控制器的VHDL代码在FGPA中的综合与实现-SDRAM controller VHDL code FGPA and implementation of integrated
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
Sdram_Control_4Port
- SDRAM控制器HDL实现，sdram为美光公司的-sdram controller
sdram_design
- SDRAM存取控制器设计书，包含标准的SDRAM读写控制功能，和自动刷新功能。对VHDL设计初学者很有帮助。密码MMCTEAM。-SDRAM access controller design books, contain standard SDRAM read and write control functions, and auto refresh function. VHDL design helpful for beginners. Password MMCTEAM.
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
Sun86
- SDRAM仿真文件，主要用于测试SDRAM的控制程序是否正确。-SDRAM simulation files, mainly used for testing control procedures SDRAM is correct.
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
testbench
- ddr sdram controller datd module source code
ceshi0326
- 高速AD采集卡应用程序及SDRAM控制器-High-speed AD acquisition card applications and SDRAM controller
sdramctrl2
- sdram controller in vhdl
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
sdram_vhd
- FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
SDRAMHDL
- SDRAM基础性控制核 很有用的 VHDL状态机实现-SDRAM control of the nuclear basic useful VHDL state machine implementation
mt48lc16m16a2
- SDram 接口verylog 程序 SDram 接口verylog 程序-SDram interface procedures verylog
tut_DE2_sdram_vhdl
- This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
sdram_vhdl_lattice
- sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
hssdrc_latest
- SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
SRAM_controller
- 对于想编写sdram控制器的人来说，值得借鉴-Sdram controller would like to prepare for the people, to learn